Adiabatic charging register circuit

ABSTRACT

An adiabatic charging register circuit comprising a plurality of n-channel MOSFET&#39;s and a plurality of p-channel MOSFET&#39;s, is operated by a clock signal which has a gradually rising and a gradually falling waveform generated by using a charge recycle power source in which charge supplied to a load is at least partially collected to said charge recycle power source, and following inequality is satisfied; 
     | V   TN   |+|V   TP   |≧VDD   
     where V TN  is threshold of an n-channel MOSFET, V TP  is threshold of a p-channel MOSFET, and VDD is output voltage of said charge recycle power source.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to an adiabatic charging registercircuit, in particular, relates to such a circuit which reduces powerconsumption associated with a clock pulse.

[0002] Conventionally, an LSI circuit includes a large number ofregister circuits, fifty thousands or more circuits. Each registercircuit comprises a D-flip flop (D-FF) or D-latch circuit. A registercircuit having a D-FF or D-latch is exemplified here.

[0003] First, a register circuit having a D-FF is described.

[0004] A D-FF has a pair of D-latch circuits. FIG. 17 shows an exampleof a D-latch circuit (page 677, Structure of Design of a computer, byPaterson, and Henesey, published by NikkeiBP). A D-latch circuit 70 inFIG. 17 has a pair of NOR circuits 71 and 72 which are cross-connectedto each other constituting a RS-FF (reset-set-flip-flop), and a pair ofAND circuits 73 and 74. It has data input terminals D, DN indifferential form, a clock input terminal CK, and data output terminalsQ, QN in differential form. Each of NOR circuits 71 and 72 operates asan inverter when one of the inputs of the same is in low state, andtherefore, a D-latch circuit 70 in FIG. 17 operates as follows.

[0005] (1) A pair of NOR circuits 71, 72 keep a previous state when aclock input terminal CK is in low state.

[0006] (2) A value of a data input terminal D is stored in a pair of NORcircuits 71, 72 when a clock input terminal CK is in high state.

[0007] A D-FF circuit 80 is constituted by using a pair of D-latchcircuits 70 as shown in FIG. 18, in which a first stage D-latch circuit70A receives a clock input CK as it is, and a second stage D-latchcircuit 70B receives a clock signal which is inversion by 180° of theclock input CK by an inverter 90. A D-FF circuit operates as follows.

[0008] (1) When a clock input CK becomes to high state, the first stageD-latch circuit 70A opens to accept a data D at an input terminal,

[0009] (2) When a clock input CK becomes to low state, the second stageD-latch circuit 70B opens and an input terminal D accepts an output O1on an output terminal Q of the first stage D-latch 70A, as an inputsignal D.

[0010]FIG. 19 shows operational wave forms of a data D, a clock inputCK, an output O1 of the first stage D-latch circuit 70A, and an outputO2 of the second stage D-latch circuit 70B. As shown in FIG. 19, theoutput O2 is switched by an input data when a clock input CK is switchedfrom high state to low state, thus, it is an edge trigger type circuit.

[0011] Conventionally, a clock signal CK is generated by using aninverter having a CMOS circuit which has a p-channel MOSFET and ann-channel MOSFET connected in series to each other, and has rectangularwave form. A load coupled with an output of a clock signal generator ischarged to power supply voltage VDD through p-channel MOSFET of aninverter when an output signal is in high state, and is discharged toground through n-channel MOSFET of an inverter when an output signal isin low state. Therefore, the power consumption P by a clock signal isP=CV²f, where f is clock frequency, V is power supply voltage, and C issum of capacitance of wires and gate capacitance which accept a clocksignal.

[0012] The capacitance of wires is lately large because of increase ofsemiconductor chip area of an integrated circuit reflecting a largescale integrated circuit, and therefore, power consumption bycharge/discharge of a clock signal occupies almost 50% of the totalpower consumption of a semiconductor chip (page 90, Technical Report oflow power LSI, Nikkei Micro-device, NikkeiBP).

[0013] Further, a large number of register circuits are used for apipeline processing in an LSI for processing moving image, and a RISCprocessor. In those devices, it is also known that power consumption bya clock system is almost the same as that by a logic system (page 8, Lowpower and high speed LSI technology, Realize Co.). That relation isindependent from operation speed, but depends upon ratio occupied by aregister circuit in an LSI.

SUMMARY OF THE INVENTION

[0014] It is an object, therefore, of the present invention to provide anew and improved register circuit by overcoming the disadvantages andlimitations of a prior register circuit.

[0015] It is also an object of the present invention to provide aregister circuit which consumes less power in a clock system.

[0016] It is further an object of the present invention to provide aregister circuit in which no short-circuit current from a power sourceto ground directly flows.

[0017] The above and other objects are attained by an adiabatic registercircuit comprising; a plurality of n-channel MOSFET transistors and aplurality of p-channel MOSFET transistors, accepting an input data, anda clock signal, and providing an output data; said clock signal being apower clock signal having a gradually rising and gradually fallingwaveform generated by using a charge recycle power source in which powersupplied to a load is at least partially collected to said chargerecycle power source; and following inequality is satisfied;

|V _(TN) |+|V _(TP) |≧VDD

[0018] where V_(TN) is threshold of said n-channel MOSFET transistor,V_(TP) is threshold of said p-channel MOSFET, and VDD is output voltageof said charge recycle power source.

[0019] Preferable, said register circuit comprises a pair of D-latchcircuits with an input of a second D-latch circuit coupled with anoutput of a first D-latch circuit, a first D-latch circuit accepts afirst power clock signal, and a second D-latch circuit accepts a secondpower clock signal which is different by 180° of the first power clocksignal.

[0020] Preferably, said D-latch circuit comprises a pair of NOR circuitswith one of the inputs of each NOR circuit being coupled with an outputof the other NOR circuit, and a pair of AND circuits each accepting aninput data in differential form and a power clock signal, and providingan output to the other input of each of said NOR circuit.

[0021] Preferably, said register circuit includes a combination logiccircuit between said pair of D-latch circuits.

[0022] Preferably, said D-latch circuit comprises a memory elementhaving a first inverter providing an output of the D-latch circuit, asecond inverter with an input coupled with an output of said firstinverter, and a first transmission gate connecting an output of thesecond inverter to an input of the first inverter, and a secondtransmission gate inserted between an input terminal and an input ofsaid first inverter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The foregoing and other objects, features, and attendantadvantages of the present invention will be appreciated as the samebecome better understood by means of the following description anddrawings wherein;

[0024]FIG. 1 is a block diagram of a D-FF circuit according to thepresent invention,

[0025]FIG. 2A is a circuit diagram of a D-latch circuit used in the D-FFcircuit in FIG. 1,

[0026]FIG. 2B shows a transistor circuit of a D-latch circuit in FIG.2A,

[0027]FIG. 2C shows operation of a conventional CMOS inverter,

[0028]FIG. 3 is a circuit diagram of a gradually rising and graduallyfalling waveform generator,

[0029]FIG. 4 shows waveforms of a power clock used in a D-FF circuit inFIG. 1,

[0030]FIG. 5 shows waveforms of another power clock used in a D-FFcircuit in FIG. 1,

[0031]FIG. 6 shows waveforms of still another power clock used in a D-FFcircuit in FIG. 1,

[0032]FIG. 7 shows operational waveforms of a D-FF circuit in FIG. 1,

[0033]FIG. 8 shows simulation result of a D-FF circuit using aconventional rectangular clock,

[0034]FIG. 9 shows simulation result of a D-FF circuit using the presentpower clock,

[0035]FIG. 10 is a block diagram of a logic system having an alternatearrangement of a D-FF circuit in FIG. 1 and a logic circuit,

[0036]FIG. 11 is a block diagram of another logic system having analternate arrangement of a D-latch circuit in FIG. 1 and a logiccircuit,

[0037]FIG. 12 is a modification of FIG. 11, and shows a pair of D-latchcircuits coupled directly with no logic circuit between them,

[0038]FIG. 13 shows operational waveforms of a circuit of FIG. 12,

[0039]FIG. 14 is another embodiment of a D-latch circuit using atransmission gate,

[0040]FIG. 15 shows waveforms of a power clock used in a circuit of FIG.14,

[0041]FIG. 16 shows the effect of the present invention,

[0042]FIG. 17 is a prior D-latch circuit,

[0043]FIG. 18 is a prior D-FF circuit, and

[0044]FIG. 19 shows operational waveforms of a D-FF circuit in FIG. 18.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] According to the present invention, a clock signal is a chargerecycle type power clock generated by using a charge recycle powersource, and having a gradually rising and gradually falling waveform,while a conventional clock signal use a rectangular clock signal. Aregister circuit using such a power clock signal has the advantage thatpower consumption in a clock system is considerably reduced as comparedwith that of a prior art, for instance, it is reduced to {fraction(1/10)} of that of a prior art. Further, when an n-channel MOSFET and ap-channel MOSFET which constitute a register circuit satisfy thefollowing condition, no short-circuit current from a power source toground is allowed;

|V _(TN) |+|V _(TP) |≧VDD

[0046] where V_(TN) is threshold of an n-channel MOSFET, V_(TP) isthreshold of a p-channel MOSFET, VDD is output voltage of a powersource.

First Embodiment

[0047]FIG. 1 is a block diagram of a D-FF circuit 20 which is a firstembodiment of the present invention. The D-FF circuit 20 comprises afirst stage D-latch circuit 10A, and a second stage D-latch circuit 10B.Each of the D-latch circuits 10A and 10B is shown in FIG. 2A by thereference numeral 10, which comprises a pair of NOR gates 11 and 12conforming an RS-FF, and a pair of AND gates 13 and 14.

[0048] The circuit of FIG. 2A is implemented by a CMOS including ap-channel MOSFET and an n-channel MOSFET, as shown in FIG. 2B, in whichan AND circuit and a NOR circuit are implemented by three p-channelMOSFET's and three n-channel MOSFET's as shown in the figure. Thus, thestructure of FIG. 2A is implemented by using two sets of a circuit ofFIG. 2B.

[0049] Now, a short-circuit current flowing from a power source VDD toground directly in a CMOS circuit is analyzed in accordance with FIG.2C. In an inverter having a series circuit of a p-channel MOSFET and ann-channel MOSFET between a power source VDD and a ground, ashort-circuit current from a power source VDD to ground flows duringtransient time of an input signal. As a power clock rises and fallsslowly, a short-circuit current during transient time would be largerthan that of a prior art which uses a prior rectangular clock. The upperportion of FIG. 2C shows the relation between an input voltage IN and anoutput voltage OUT, and the lower portion of FIG. 2C shows the relationbetween an input voltage IN and a short-circuit current. The maximumshort-circuit current Imax is:

Imax=(β_(n)/2)((VDD−|V _(TN) |−|V _(TP)|)/(1+{square root}{square rootover (β_(n)/β_(p))}))² VDD>|V _(TN) |+|V _(TP)|

[0050] Imax=0

VDD≧|V _(TN) |+|V _(TP)|

[0051] where β_(n)=μ_(n) Cox(W/L)

[0052] μ_(n) is mobility

[0053] W is channel width of a MOSFET

[0054] L is channel length of a MOSFET

[0055] Cox is oxide capacitance per unit area

[0056] Therefore, a short-circuit current from a power source to groundis zero, even if a gradually rising and gradually falling power clock isused, when VDD≧|V_(TN)|+|V_(TP)| is satisfied.

[0057] According to the present invention, a threshold value V_(TN) ofan n-channel MOSFET and a threshold value V_(TP) of a p-channel MOSFETis designed high so that the following inequality is satisfied;

|V _(TN) |+|V _(TP) |≧V _(DD)

[0058] where V_(TN) is a threshold of an n-channel MOSFET used in NORgates 11 and 12, and AND gates 13 and 14. V_(TP) is a threshold of ap-channel MOSFET used in NOR gates 11 and 12, and AND gates 13 and 14,and VDD is power source voltage. That condition allows no short-circuitcurrent from a power source to ground of a logic gate in a D-latchcircuit 10.

[0059] Further, according to the present invention, a clock inputterminal PCK of a first stage D-latch circuit 10A in a D-FF 20 receivesa first power clock PCK1 which is generated by a charge recycle typepower source, and has wave-form which rises and falls slowly orgradually, and a clock input terminal PCK of a second stage D-latchcircuit 10B in a D-FF 20 receives a second power clock PCK2 which hasdifferent phase by 180° of that of the first power clock PCK1.

[0060] The power clocks PCK1 and PCK2 may be generated by using agradually rising and gradually falling waveform generator 30 constitutedby a switched capacitor circuit as shown in FIG. 3 (1999 SSDM page 444),or an LC resonance circuit (not shown). In FIG. 3, T0-T4, T0′-T4′ are atransmission gate, C1-C3 are a capacitor. A gradually rising andgradually falling waveform generator 30 provides a pair of power clocksPCK1 and PCK2 having a gradually rising and gradually falling waveformby conducting a pair of transmission gates sequentially in the followingsequence. $\begin{matrix}\left. \left( {{T0},{T0}^{\prime}} \right)\rightarrow\left. \left( {{T1},{T1}^{\prime}} \right)\rightarrow\left. \left( {{T2},{T2}^{\prime}} \right)\rightarrow\left. \left( {{T3},{T3}^{\prime}} \right)\rightarrow\left. \left( {{T4},{T4}^{\prime}} \right)\rightarrow \right. \right. \right. \right. \right. \\\left. \left( {{T3},{T3}^{\prime}} \right)\rightarrow\left. \left( {{T2},{T2}^{\prime}} \right)\rightarrow\left. \left( {{T1},{T1}^{\prime}} \right)\rightarrow\left. \left( {{T0},{T0}^{\prime}} \right)\rightarrow\left. \left( {{T1},{T1}^{\prime}} \right)\rightarrow \right. \right. \right. \right. \right.\end{matrix}$

[0061] Assuming that VDD=1V, |V_(TN)|=|V_(TP)|=0.7V, the operation ofthe first stage D-latch circuit 10A and the second stage D-latch circuit10B is shown in FIG. 4. When the amplitude of the power clocks PCK1 andPCK2 is higher than 0.7V, the D-latch circuit 10A or 10B accepts aninput data, and keeps the previous status when the amplitude of thepower clocks PCK1 and PCK2 is lower than 0.7V.

[0062]FIGS. 5 and 6 show wave-forms of power clocks PCK1 and PCK2 havingdifferent duty ratio from each other.

[0063] In those figures, the period T_(FF) shows the time from datainput to data outut in a D-FF circuit 20, and the period Tcombinationshows the allowable delay time allowed to a combination logic circuitcoupled with an output or an input of a D-FF circuit 20.

[0064] A D-FF circuit driven by power clocks PCK1 and PCK2 is called anadiabatic charging D-FF circuit, since power consumption of power clocksare not consumed but are returned to a power supply. The adiabaticcharging D-FF circuit has the following features.

[0065] (1) It has cross-wired NOR gates in static operation which isstable as compared with dynamic operation. Static operation has anoutput equal to VDD or 0, while dynamic operation has not only an outputof VDD or 0, but also an open output which is not VDD nor 0.

[0066] (2) No data goes directly from input to output of a D-FF circuit,since a first stage D-latch 10A and a second stage D-latch 10B do nottake data simultaneously.

[0067] (3) Both D-latch circuits 10A and 10B have a period of storagemode simultaneously. In that case, each D-latch circuit 10A and 10Bstores data independently.

[0068] (4) The time T_(FF) is larger than T_(FF) of a prior D-FFcircuit.

[0069] (5) The power consumption is less than {fraction (1/10)} of thatusing a conventional rectangular clock signal, since power clocks PCK1and PCK2 are used.

[0070] (6) It is compatible with a prior D-FF. In other words, aconventional D-FF circuit constituted by a CMOS circuit using arectangular clock signal can be substituted with an adiabatic chargingD-FF circuit using a charge recycle type power source.

[0071]FIG. 7 shows the operation of an adiabatic charging D-FF circuitof FIG. 1. It is noted that an input data D is taken when a power clockPCK1 changes from high to low, and the data thus taken is kept for aperiod of the PCK2 (see an output wave form O2).

[0072]FIGS. 8 and 9 show the simulation result using a simulationsoftware HSPICE. FIG. 8 shows the result of a conventional D-FF 80 inFIG. 18 when a conventional rectangular clock CK is used, and FIG. 9shows the result of the present D-FF 20 in FIG. 1 when the present powerclocks PCK1 and PCK2 are used. The power clock PCK2 is not shown sinceit is the same as PCK1 but different phase by 180° phase. In thesimulation, it is assumed that the gate length of an n-channel MOSFETand a P-channel MOSFET is 0.25 μm, the gate width of a p-channel MOSFETis 9 μm, the gate width of an n-channel MOSFET is 6 μm, the threshold is|V_(TN)|=|V_(TP)|=0.3V, the power supply voltage is VDD=0.5 V, and theperiod of a clock signal (PCK1, PCK2, CK) is 100 nS (f=10 MHz).

[0073] The simulation result shows that outputs of a D-FF circuit whenPCK1 and PCK2 are used are the same as those when a conventional clockCK is used.

[0074] The power consumption by a D-FF circuit with a constant powersupply voltage is 320 nW in both a conventional D-FF circuit using aCMOS, and the present adiabatic charging type D-FF circuit. No increasein power consumption by a short-circuit current occurs as noshort-circuit current flows. The power consumption by a conventionalrectangular clock signal CK is 310 nW, while the power consumption bythe present power clock signals PCK1 and PCK2 is only 23 nW. Thus, thepower consumption by the adiabatic power clock signals is less than{fraction (1/10)} of that of a conventional clock signal.

[0075]FIG. 10 shows a logic system having alternate arrangement of aD-FF circuit 20A through 20C of the D-FF circuit 20 in FIG. 1, andcombination logic circuit 40A through 40C. It should be noted that theprocess time in a logic circuit 40A through 40C is less than saidTcombination.

Second Embodiment

[0076]FIG. 11 shows the second embodiment according to the presentinvention. The feature of FIG. 11 is an alternate arrangement of aD-latch circuit 10A through 10D of the D-latch circuit in FIG. 2 and acombination logic circuit 40A through 40D. No concept of the time T_(FF)exists in this embodiment, and the allowable delay time allowed to eachcombination logic circuit 40A through 40D is the same as the allowedtime between latch circuits using a conventional rectangular clocksignal.

[0077]FIG. 12 is a modification of FIG. 11. In FIG. 12, a pair ofD-latch circuits 10A and 10B are coupled directly together with nocombination logic circuit between the D-latch circuits, and theoperational wave forms of FIG. 12 are shown in FIG. 13, which is almostthe same as those of FIG. 7 which shows the operation of FIG. 1, exceptthat an input data I is slightly modified so that an input data Ichanges from high to low at time t1 when a power clock PCK1 is higherthan threshold value, the wave form of the input signal I appears in anoutput O1.

Third Embodiment

[0078]FIG. 14 shows the third embodiment according to the presentinvention. In this embodiment, a latch circuit is comprised of a memorycircuit having a pair of inverters 60A and 60B, and a transmission gate50B, and another transmission gate 50A connected to an input side of thetransmission gate 50B. Four power clocks PCK1, PCK2, PCK3 and PCK4 areused. PCK1 and PCK2 are applied to the transmission gate 50A, and havethe opposite relations with each other. PCK3 and PCK4 are applied to thetransmission gate 50B, and have the opposite relations with each other.PCK1 and PCK2 are shifted by 180° from PCK3 and PCK4, respectively.

[0079]FIG. 15 shows wave forms of power clocks PCK1 through PCK4.

[0080] (Consideration of a D-latch circuit)

[0081] Two kinds of D-latch circuits are possible, one is an RS-FF typeas shown in FIG. 2, and the other is a transmission gate type as shownin FIG. 14.

[0082] An RS-FF type takes static operation for input and storage of adata, and operates correctly even for slow speed operation. On the otherhand, a transmission gate type circuit operates dynamically, and is notsuitable to very slow speed operation.

[0083] As for a number of transistors which receive a clock signal, anRS-FF type circuit has four transistors (two transistors in each ANDgate), and a transmission gate type circuit has six transistors (eachtransmission gate has two transistors and two transistors are used forinverting a clock signal. There are two transmission gates 50A and 50B,thus, six transistors are required). Thus, an RS-FF type circuitrequires less number of transistors as far as a clock signal concerns,although an RS-FF type circuit requires more number of transistors intotal than a transmission gate type circuit, and therefore, powerconsumption in an RS-FF type is smaller (C. Svensson and D. Liu, LowPower Design Methodologies, eds. J. M. Rabaey and M. Pedram (KluwerAcademic Publisheres, 1996) Chap.3, page 37).

[0084] The choice of an RS-FF type circuit or a transmission gate typecircuit as a adiabatic charging reversible logic circuit should bedesigned base upon an object of a circuit, considering above analysis.

[0085] (The use in sub-threshold region)

[0086] In a specific condition, the current adiabatic charging registercircuit can operates in weak inversion region with power supply voltagelower than threshold voltage (sub-threshold region; |V_(TP)|>VDD and|V_(TN)|>VDD), like a prior CMOS circuit. It can be applied to slowspeed operation LSI in sub-threshold region such as an environmentsensor, or a living body sensor.

[0087] (Effect of the invention)

[0088] As described above, according to an adiabatic charging registercircuit of the present invention, power consumption consumed in a clocksystem is reduced approximately {fraction (1/10)} of that of aconventional CMOS register circuit (FIG. 16). FIG. 16 shows that thepower consumption by a clock signal and the power consumption of a logiccircuit in a prior art are almost the same as each other, on the otherhand, the power consumption by a clock signal in the present inventionis only {fraction (1/10)} of that of a prior art. Therefore, althoughthe power consumption by a logic circuit in the present invention is thesame as that of a prior art, the total power consumption including aclock system and a logic circuit in the present invention isconsiderably smaller than that of a prior art.

[0089] Further, the present adiabatic charging register circuit iscompatible with a conventional CMOS type register circuit. It is enoughonly to substitute an adiabatic charging type register circuit with aconventional CMOS type register circuit. Thus, the design of a circuitis quite simple.

[0090] From the foregoing, it should be appreciated that a new andimproved adiabatic charging type register circuit has been found. Itshould be understood of course that the embodiments disclosed are merelyillustrative and are not intended to limit the scope of the invention.Reference should be made to the appended claims, therefore, to indicatethe scope of the invention.

What is claimed is:
 1. A register circuit having a plurality ofn-channel MOSFET transistors and a plurality of p-channel MOSFETtransistors, accepting an input data, and a clock signal, and providingan output data, said clock signal being a power clock signal having agradually rising and gradually falling waveform generated by using acharge recycle power source in which power supplied to a load is atleast partially collected to said charge recycle power source, andfollowing inequality is satisfied; |V _(TN) |+|V _(TP) |≧VDD whereV_(TN) is threshold of said n-channel MOSFET transistor, V_(TP) isthreshold of said p-channel MOSFET, and VDD is output voltage of saidcharge recycle power source.
 2. A register circuit according to claim 1,wherein said register circuit comprises a pair of D-latch circuits withan input of a second D-latch circuit coupled with an output of a firstD-latch circuit, a first D-latch circuit accepts a first power clocksignal, and a second D-latch circuit accepts a second power clock signalwhich is different by 180° phase of the first power clock signal.
 3. Aregister circuit according to claim 2, wherein said D-latch circuitcomprises a pair of NOR circuits with one of the inputs of each NORcircuit being coupled with an output of the other NOR circuit, and apair of AND circuits each accepting an input data in differential formand a power clock signal, and providing an output to the other input ofeach of said NOR circuit.
 4. A register circuit according to claim 1,wherein said register circuit includes a combination logic circuitbetween said pair of D-latch circuits.
 5. A register circuit accordingto claim 1, wherein said D-latch circuit comprises a memory elementhaving a first inverter providing an output of the D-latch circuit, asecond inverter with an input coupled with an output of said firstinverter, and a first transmission gate connecting an output of thesecond inverter to an input of the first inverter, and a secondtransmission gate inserted between an input terminal and an input ofsaid first inverter.